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CYS25G0101DX
SONET OC-48 Transceiver
Features
I I I I I I I I I
Functional Description
The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full SONET compliance.
SONET OC-48 operation Bellcore and ITU jitter compliance 2.488 GBaud serial signaling rate Multiple selectable loopback or loop through modes Single 155.52 MHz reference clock Transmit FIFO for flexible data interface clocking 16-bit parallel-to-serial conversion in transmit path Serial-to-16-bit parallel conversion in receive path Synchronous parallel interface E LVPECL compliant E HSTL compliant Internal transmit and receive phase-locked loops (PLLs) Differential CML serial input E 50 mV input sensitivity E 100 Internal termination and DC restoration Differential CML serial output E Source matched for 50 transmission lines (100 differential transmission lines) Direct interface to standard fiber optic modules Less than 1.0W typical power 120-pin 14 mm x 14 mm TQFP Standby power saving mode for inactive loops 0.25 BiCMOS technology Pb-free packages available
Transmit Path
New data is accepted at the 16-bit parallel transmit interface at a rate of 155.52 MHz. This data is passed to a small integrated FIFO to allow flexible transfer of data between the SONET processor and the transmit serializer. As each 16-bit word is read from the transmit FIFO, it is serialized and sent out to the high speed differential line driver at a rate of 2.488 Gbits/second.
Receive Path
As serial data is received at the differential line receiver, it is passed to a clock and data recovery (CDR) PLL that extracts a precision low jitter clock from the transitions in the data stream. This bit rate clock is used to sample the data stream and receive the data. Every 16-bit times, a new word is presented at the receive parallel interface along with a clock.
I I
I
Parallel Interface
The parallel I/O interface supports high speed bus communications using HSTL signaling levels to minimize both power consumption and board landscape. The HSTL outputs are capable of driving unterminated transmission lines of less than 70 mm and terminated 50 transmission lines of more than twice that length. The CYS25G0101DX Transceiver's parallel HSTL I/O can also be configured to operate at LVPECL signaling levels. This is done externally by changing VDDQ, VREF and creating a simple circuit at the termination of the transceiver's parallel output interface.
I I I I I I
Cypress Semiconductor Corporation Document Number: 38-02009 Rev. *K
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 27, 2007
CYS25G0101DX
Logic Block Diagram
(155.52 MHz) TXCLKI TXD[15:0] FIFO_RST 16 16 Output Register
/16
FIFO_ERR
TXCLKO
(155.52 MHz) REFCLK
(155.52 MHz) RXCLK
RXD[15:0]
Input Register
TX PLL X16
FIFO
Shifter
/16
TX Bit-Clock Shifter
Recovered Bit-Clock RX CDR PLL Lock-to-Ref Retimed Data
LOOPTIME DIAGLOOP
LINELOOP LOOPA
Lock-to-Data/ Clock Control Logic
OUT
PWRDN LOCKREF
SD
LFI
RESET
IN
Document Number: 38-02009 Rev. *K
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CYS25G0101DX
Clocking
The source clock for the transmit data path is selectable from either the recovered clock or an external BITS (Building Integrated Timing Source) reference clock. The low jitter of the CDR PLL allows loop timed operation of the transmit data path meeting all Bellcore and ITU jitter requirements. Multiple loopback and loop through modes are available for both diagnostic and normal operation. For systems containing redundant SONET rings that are maintained in standby, the CYS25G0101DX may also be dynamically powered down to conserve system power. Figure 1. CYS25G0101DX System Connections SONET Data Processor
Transmit Data Interface 16 16
CYS25G0101DX
TXD[15:0] TXCLKI FIFO_RST FIFO_ERR TXCLKO RXD[15:0] RXCLK LOOPTIME DIAGLOOP LOOPA LINELOOP RESET PWRDN LOCKREF LFI
System or Telco Bus
REFCLK
2
155.52 MHz BITS Time Reference
Host Bus Interface
Receive Data Interface
Data & Clock Direction Control
IN+ IN- SD OUT- OUT+
Serial Data
Serial Data
RD+ RD- SD TD- TD+
Optical XCVR
Optical Fiber Links
Status and System Control
Document Number: 38-02009 Rev. *K
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CYS25G0101DX
Pin Configuration
The pin configuration for 120-pin Thin Quad Flatpack follows. [1, 2] Figure 2. 120-Pin Thin Quad Flatpack Pin Configuration
VCCQ \NC* RXCP1 VSSQ \NC* VSSQ \NC*
Top View
CM_SER VCCQ VCCQ VSSQ VSSQ VCCQ VCCQ VCCQ
O UT+ O UT-
RXCN2
RXCN1
RXCP2
VCCQ
VSSQ
NC VSSQ
VSSQ
IN+
IN-
NC
NC
NC
NC 93
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
92
NC
91
NC
LFI RESET DIAG LOOP LINELOO P LOOPA VSSN VCCN VSSN VSSN SD LOCKREF R XD[0] R XD[1] R XD[2] R XD[3] VSSN VDDQ R XD[4] R XD[5] R XD[6] R XD[7] VSSN VDDQ RXCLK VSSN VDDQ NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CYS25G0101DX
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75
NC VCCQ VSSQ REFCLK+ REFCLK- NC LO OPTIME PW RDN VSSN VCCN VSSN TXCLKO VSSN VDDQ TXD[0] TXD[1] TXD[2] TXD[3] VCCQ VSSQ VCCN VSSN TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] TXD[10] TXD[11]
74 73 72 71 70 69 68 67 66 65 64 63 62 61 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VCCQ NC
VSSQ
VCC N
RXD[12]
RXD[13]
RXD[15]
TXD[15]
TXD[14]
TXD[13]
TXD[12]
RXD[14]
VC CQ RXD[8]
FIFO_RST
TXCLKI
VD DQ
VDDQ
VCC N
VSSN
VSSN
VSSQ
VSSN
NC
Notes 1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of the device. 2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ. Use VCCQ for compatibility with next generation of OC-48 SERDES devices.
Document Number: 38-02009 Rev. *K
FIFO_ERR
RXD[10] RXD[11]
RXD[9]
VSSN
VREF
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CYS25G0101DX
Pin Descriptions
CYS25G0101DX OC-48 SONET Transceiver Pin Name TXD[15:0] TXCLKI I/O Characteristics Signal Description Transmit Path Signals HSTL inputs, Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI. TXD[15] is the most sampled by TXCLKI significant bit (the first bit transmitted). HSTL Clock input Parallel Transmit Data Input Clock. The TXCLKI is used to transfer the data into the input register of the serializer. The TXCLKI samples the data, TXD [15:0], on the rising edge of the clock cycle. Transmit Clock Output. Divide by 16 of the selected transmit bit rate clock. It is used to coordinate byte wide transfers between upstream logic and the CYS25G0101DX. Reference Voltage for HSTL Parallel Input Bus. VDDQ/2.[3]
TXCLKO VREF
HSTL Clock output Input Analog Reference HSTL output, synchronous HSTL Clock output Analog Analog Analog Analog Analog Differential LVPECL input LVTTL output
Receive Path Signals RXD[15:0] RXCLK CM_SER RXCN1 RXCN2 RXCP1 RXCP2 REFCLK Parallel Receive Data Output. These outputs change following RXCLK. RXD[15] is the most significant bit of the output word and is received first on the serial interface. Receive Clock Output. Divide by 16 of the bit rate clock extracted from the received serial stream. RXD [15:0] is clocked out on the falling edge of the RXCLK. Common Mode Termination. Capacitor shunt to VSS for common mode noise. Receive Loop Filter Capacitor (Negative). Receive Loop Filter Capacitor (Negative). Receive Loop Filter Capacitor (Positive). Receive Loop Filter Capacitor (Positive). Reference Clock. This clock input is used as the timing reference for the transmit and receive PLLs. A derivative of this input clock is used to clock the transmit parallel interface. The reference clock is internally biased enabling for an AC coupled clock signal. Line Fault Indicator. When LOW, this signal indicates that the selected receive data stream is detected as invalid by either a LOW input on SD or by the receive VCO operated outside its specified limits. Reset for all logic functions except the transmit FIFO. Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. The SD needs to be connected to an external optical module to indicate a loss of received optical power. Transmit FIFO Error. When HIGH, the transmit FIFO has either under or overflowed. When this occurs, the FIFO's internal clearing mechanism clears the FIFO within nine clock cycles. In addition, FIFO_RST is activated at device power up to ensure that the in and out pointers of the FIFO are set to maximum separation. Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are set to maximum separation. FIFO_RST is activated at device power up to ensure that the in and out pointers of the FIFO are set to maximum separation. When the FIFO is reset, the output data is a 1010... pattern. Device Power Down. When LOW, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated.
Device Control and Status Signals
LFI
RESET LOCKREF SD
LVTTL input LVTTL input LVTTL input
FIFO_ERR
LVTTL output
FIFO_RST
LVTTL input
PWRDN
LVTTL input
Note 3. VREF equals to (VCC - 1.33V) if interfacing to a parallel LVPECL interface.
Document Number: 38-02009 Rev. *K
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CYS25G0101DX
CYS25G0101DX OC-48 SONET Transceiver (continued) Pin Name DIAGLOOP I/O Characteristics LVTTL input Signal Description Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive clock and data recovery. It is then presented at the RXD[15:0] outputs. When LOW, received serial data is routed through the receive clock and data recovery. It is then presented at the RXD[15:0] outputs. Line Loopback Control. When HIGH, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data passed to the OUT line driver is controlled by LOOPA. When both LINELOOP and LOOPA are LOW, the data passed to the OUT line driver is generated in the transmit shifter. Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial data is looped back from receive input buffer to transmit output buffer but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the OUT line driver is controlled by LINELOOP. Loop Time Mode. When HIGH, the extracted receive bit clock replaces transmit bit clock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock. Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable of driving terminated 50 transmission lines or commercial fiber optic transmitter modules. Differential Serial Data Input. This differential input accepts the serial data stream for deserialization and clock extraction. +3.3V supply (for digital and low speed IO functions) Signal and power ground (for digital and low speed IO functions) +3.3V quiet power (for analog functions) Quiet ground (for analog functions) +1.5V supply for HSTL outputs[4] HIGH, the present input clock phase, relative to TXCLKO, is set. Once set, the input clock is allowed to skew in time up to half a character period in either direction relative to REFCLK (that is, 180). This time shift allows the delay path of the character clock (relative to REFLCK) to change due to operating voltage and temperature not affecting the desired operation. FIFO_RST is an asynchronous input. FIFO_ERR is the transmit FIFO Error indicator. When HIGH, the transmit FIFO has either under or overflowed. The FIFO is externally reset to clear the error indication; or if no action is taken, the internal clearing mechanism clears the FIFO in nine clock cycles. When the FIFO is being reset, the output data is 1010. Loop Control Signals
LINELOOP
LVTTL input
LOOPA
LVTTL input
LOOPTIME Serial I/O OUT IN Power VCCN VSSN VCCQ VSSQ VDDQ
LVTTL input
Differential CML output Differential CML input Power Ground Power Ground Power
CYS25G0101DX Operation
The CYS25G0101DX is a highly configurable device designed to support reliable transfer of large quantities of data using high speed serial links. It performs necessary clock and data recovery, clock generation, serial-to-parallel conversion, and parallel-to-serial conversion. CYS25G0101DX also provides various loopback functions.
CYS25G0101DX Transmit Data Path
Operating Modes
The transmit path of the CYS25G0101DX supports 16-bit wide data paths.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a 155.52 MHz external clock at the REFCLK input. It multiplies that clock by 16 to generate a bit rate clock for use by the transmit shifter. The operating serial signaling rate and allowable range of REFCLK frequencies is listed in Table 7 on page 11. The REFCLK phase noise limits to meet SONET compliancy are shown in Figure 6 on page 13. The REFCLK input is a standard LVPECL input.
Phase Align Buffer
Data from the input register is passed to a phase align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. Initialization of the phase align buffer takes place when the FIFO_RST input is asserted LOW. When FIFO_RST is returned
Note 4. VDDQ equals VCC if interfacing to a parallel LVPECL interface.
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CYS25G0101DX
Serializer
The parallel data from the phase align buffer is passed to the Serializer that converts the parallel data to serial data. It uses the bit rate clock generated by the Transmit PLL clock multiplier. TXD[15] is the most significant bit of the output word and is transmitted first on the serial interface.
the frequency of the clock that drives the REFCLK signal of the remote transmitter to ensure a lock to the incoming data stream. For systems using multiple or redundant connections, the LFI output can be used to select an alternate data stream. When an LFI indication is detected, external logic toggles selection of the input device. When such a port switch takes place, it is necessary for the PLL to reacquire lock to the new serial stream.
Serial Output Driver
The Serial Interface Output Driver makes use of high performance differential Current Mode Logic (CML) to provide a source matched driver for the transmission lines. This driver receives its data from the Transmit Shifters or the receive loopback data. The outputs have signal swings equivalent to that of standard LVPECL drivers and are capable of driving AC coupled optical modules or transmission lines.
External Filter
The CDR circuit uses external capacitors for the PLL filter. A 0.1 F capacitor needs to be connected between RXCN1 and RXCP1. Similarly a 0.1 F capacitor needs to be connected between RXCN2 and RXCP2. The recommended packages and dielectric material for these capacitors are 0805 X7R or 0603 X7R.
CYS25G0101DX Receive Data Path
Serial Line Receivers
A differential line receiver, IN, is available for accepting the input serial data stream. The serial line receiver inputs accommodate high wire interconnect and filtering losses or transmission line attenuation (VSE > 25 mV, or 50 mV peak-to-peak differential). It can be AC coupled to +3.3V or +5V powered fiber optic interface modules. The common mode tolerance of these line receivers accommodates a wide range of signal termination voltages.
Deserializer
The CDR circuit extracts bits from the serial data stream and clocks these bits into the Deserializer at the bit clock rate. The Deserializer converts serial data into parallel data. RXD[15] is the most significant bit of the output word and is received first on the serial interface.
Loopback Timing Modes
CYS25G0101DX supports various described in the following sections. loopback modes, as
Lock to Data Control
Line Receiver routed to the clock and data recovery PLL is monitored for: I status of signal detect (SD) pin I status of LOCKREF pin. This status is presented on the Line Fault Indicator (LFI) output, that changes asynchronously in the cases in which SD or LOCKREF go from HIGH to LOW. Otherwise, it changes synchronously to the REFCLK.
Facility Loopback (Line Loopback with Retiming) When the LINELOOP signal is set HIGH, the Facility Loopback mode is activated and the high speed serial receive data (IN) is presented to the high speed transmit output (OUT) after retiming. In Facility Loopback mode, the high speed receive data (IN) is also converted to parallel data and presented to the low speed receive data output pins (RXD[15:0]). The receive recovered clock is also divided down and presented to the low-speed clock output (RXCLK). Equipment Loopback (Diagnostic Loopback with Retiming) When the DIAGLOOP signal is set HIGH, transmit data is looped back to the RX PLL, replacing IN. Data is looped back from the parallel TX inputs to the parallel RX outputs. The data is looped back at the internal serial interface and goes through transmit shifter and the receive CDR. SD is ignored in this mode. Line Loopback Mode (Non-retimed Data) When the LOOPA signal is set HIGH, the RX serial data is directly buffered out to the transmit serial data. The data at the serial output is not retimed. Loop Timing Mode When the LOOPTIME signal is set HIGH, the TX PLL is bypassed and the receive bit rate clock is used for the transmit side shifter.
Clock Data Recovery
The extraction of a bit rate clock and recovery of data bits from received serial stream is performed by a Clock Data Recovery (CDR) block. The clock extraction function is performed by high performance embedded phase-locked loop (PLL) that tracks the frequency of the incoming bit stream and aligns the phase of the internal bit rate clock to the transitions in the selected serial data stream. CDR accepts a character rate (bit rate * 16) reference clock on the REFCLK input. This REFCLK input is used to ensure that the VCO (within the CDR) is operating at the correct frequency (rather than some harmonic of the bit rate), to improve PLL acquisition time and to limit unlocked frequency excursions of the CDR VCO when no data is present at the serial inputs. Regardless of the type of signal present, the CDR attempts to recover a data stream from it. If the frequency of the recovered data stream is outside the limits set by the range controls, the CDR PLL tracks REFCLK instead of the data stream. When the frequency of the selected data stream returns to a valid frequency, the CDR PLL is allowed to track the received data stream. The frequency of REFCLK must be within 100 ppm of
Reset Modes
ALL logic circuits in the device are reset using RESET and FIFO_RST signals. When RESET is set LOW, all logic circuits except FIFO are internally reset. When FIFO_RST is set LOW, the FIFO logic is reset.
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CYS25G0101DX
Power Down Mode
CYS25G0101DX provides a global power down signal PWRDN. When LOW, this signal powers down the entire device to a minimal power dissipation state. RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low power dissipation.
DC Input Voltage ................................... -0.5V to VCC + 0.5V Static Discharge Voltage........................................... > 1100V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA
Power Up Requirements
Power supply sequencing is not required if you are configuring VDDQ=3.3V and all power supplies pins are connected to the same 3.3V power supply. Power supply sequencing is required if you are configuring VDDQ=1.5V. Power is applied in the following sequence: VCC (3.3) followed by VDDQ (1.5). Power supply ramping may occur simultaneously as long as the VCC/VDDQ relationship is maintained.
LVPECL Compliance
The CYS25G0101DX HSTL parallel I/O can be configured to LVPECL compliance with slight termination modifications. On the transmit side of the transceiver, the TXD[15:0] and TXCLKI are made LVPECL compliant by setting VREF (reference voltage of a LVPECL signal) to VCC - 1.33V. To emulate an LVPECL signal on the receiver side, set the VDDQ to 3.3V and the transmission lines needs to be terminated with the Thevenin equivalent of Z at LVPECL ref. The signal is then attenuated using a series resistor at the driver end of the line to reduce the 3.3V swing level to an LVPECL swing level (see Figure 10). This circuit needs to be used on all 16 RXD[15:0] pins, TXCLKO, and RXCLK. The voltage divider is calculated assuming the system is built with 50 transmission lines.
Operating Range
Range Commercial Industrial Ambient Temperature 0 to +70 C C VDDQ VCC
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. -65 to +150 C C Ambient Temperature with Power Applied ............................................ -55 to +125 C C VCC Supply Voltage to Ground Potential ........-0.5V to +4.2V VDDQ Supply Voltage to Ground Potential ......-0.5V to +4.2V DC Voltage Applied to HSTL Outputs in High Z State ..................................... -0.5V to VDDQ + 0.5V DC Voltage Applied to Other Outputs in High Z State ....................................... -0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW) ................. 30 mA Table 1. DC Specifications--LVTTL Parameter LVTTL Outputs VOHT VOLT IOS LVTTL Inputs VIHT VILT IIHT IILT Capacitance CIN Input Capacitance Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Description
1.4V to 1.6V[4] 3.3V 10%
-40 to +85 1.4V to 1.6V[4] 3.3V 10% C C
Test Conditions VCC = Min, IOH = -10.0 mA VCC = Min, IOL = 10.0 mA VOUT = 0V Low = 2.1V, High = VCC + 0.5V Low = -3.0V, High = 0.8 VCC = Max, VIN = VCC VCC = Max, VIN = 0V VCC = Max, at f = 1 MHz
Min 2.4
Max
Unit V
0.4 -20 2.1 -0.3 -90 VCC - 0.3 0.8 50 -50 5
V mA V V
A A
pF
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CYS25G0101DX
Table 2. DC Specifications--Power Parameter Power ICC1 ISB Active Power Supply Current Standby Current 300 347 5 mA mA Description Test Conditions Typ Max Unit
Table 3. DC Specifications--Differential LVPECL Compatible Inputs (REFCLK) The DC Specifications--Differential LVPECL Compatible Inputs (REFCLK) follow. [5] Parameter VINSGLE VDIFFE VIEHH VIELL IIEH IIEL Capacitance CINE Input Capacitance 4 pF Description Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current VIN = VIEHH Max. VIN = VIELL Min. -200 Test Conditions Min 200 400 VCC - 1.2 VCC - 2.0 Max 600 1200 VCC - 0.3 VCC - 1.45 750 Unit mV mV V V A A
Table 4. DC Specifications--Differential CML The DC Specifications--Differential CML follow. [5] Parameter VOHC VOLC VDIFFOC VSGLCO VINSGLC VDIFFC VICHH VICLL Description Output HIGH Voltage (VCC Referenced) Output LOW Voltage (VCC Referenced) Output Differential Swing Output Single-ended Voltage Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage
Figure 3. Differential Waveform Definition V (+ ) V SGL V (-) VD 0 .0 V V D IF F = V (+ )-V (-)
Test Conditions
Min
Max
Unit V V mV mV mV mV V V
Transmitter CML compatible Outputs 100 differential load VCC - 0.5 VCC - 0.15 100 differential load VCC - 1.2 VCC - 0.7 100 differential load 100 differential load 560 280 25 50 1.2 1600 800 1000 2000 VCC
Receiver CML compatible Inputs
5. See Figure 3 for differential waveform definition.
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CYS25G0101DX
Table 5. DC Specifications--HSTL Parameter HSTL Outputs Description Test Conditions Min Max Unit
VOHH VOLH IOSH
HSTL Inputs
Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input Capacitance
VCC = min, IOH= -4.0 mA VCC = min, IOL= 4.0 mA VOUT = 0V
VDDQ - 0.4 0.4 100 VREF + 0.13 VDDQ + 0.3 -0.3 VREF - 0.1
V V mA V V
A A
VIHH VILH IIHH IILH
Capacitance
VDDQ = max, VIN = VDDQ VDDQ = max, VIN = 0V VDDQ = max, at f = 1 MHz
50 -40 5
CINH
pF
AC Waveforms
3.0V Vth = 1.4V GND < 1 ns 2.0V 0.8V 3.0V 2.0V 0.8V Vth = 1.4V < 1 ns 80% 20% < 150 ps VICLL VICHH 80% 20% < 150 ps
(a) LVTTL Input Test Waveform
VIHH Vth = 0.75V VIHL < 1 ns < 1 ns 80% 20% 80% 20%
(b) CML Input Test Waveform
VIEHH 80% Vth = 0.75V 20% < 1.0 ns VIELL 80% 20% < 1.0 ns
(c) HSTL Input Test Waveform
(d) LVPECL Input Test Waveform
AC Test Loads
3.3V OUTPUT R1 = 330 R2 = 510 CL 10 pF (Includes fixture and probe capacitance) CL R2 R1 OUT+ OUT- RL RL = 100 OUTPUT R1 = 100 R2 = 100 CL 7 pF (Includes fixture and probe capacitance) CL R2 1.5V R1
(a) TTL AC Test Load
(b) CML AC Test Load
(c) HSTL AC Test Load
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CYS25G0101DX
AC Specifications
Table 6. AC Specifications--Parallel Interface Parameter Description Min Max Unit
tTS tTXCLKI tTXCLKID tTXCLKIR tTXCLKIF tTXDS tTXDH tTOS tTXCLKO tTXCLKOD tTXCLKOR tTXCLKOF tRS tRXCLK tRXCLKD tRXCLKR tRXCLKF tRXDS tRXDH tRXPD
TXCLKI Frequency (must be frequency coherent to REFCLK) TXCLKI Period TXCLKI Duty Cycle TXCLKi Rise Time TXCLKi Fall Time Write Data Setup to of TXCLKI Write Data Hold from of TXCLKI TXCLKO Frequency TXCLKO Period TXCLKO Duty Cycle TXCLKO Rise Time TXCLKO Fall Time RXCLK Frequency RXCLK Period RXCLK Duty Cycle RXCLK Rise Time[6] RXCLK Fall Time[6] Recovered Data Setup with reference to of RXCLK Recovered Data Hold with reference to of RXCLK Valid Propagation Delay
154.5 6.38 40 0.3 0.3 1.5 0.5 154.5 6.38 43 0.3 0.3 154.5 6.38 43 0.3 0.3 2.2 2.2 -1.0
156.5 6.47 60 1.5 1.5
MHz ns % ns ns ns ns
156.5 6.47 57 1.5 1.5 156.5 6.47 57 1.5 1.5
MHz ns % ns ns MHz ns % ns ns ns ns
1.0
ns
Table 7. AC Specifications--REFCLK
The AC Specifications--REFCLK follow. [7]
Parameter Description Min Max Unit
tREF tREFP tREFD tREFT tREFR tREFF
REFCLK Input Frequency REFCLK Period REFCLK Duty Cycle REFCLK Frequency Tolerance -- (relative to received serial data)[8] REFCLK Rise Time REFCLK Fall Time
154.5 6.38 35 -100 0.3 0.3
156.5 6.47 65 +100 1.5 1.5
MHz ns % ppm ns ns
Table 8. AC Specifications-CML Serial Outputs Parameter Description Min Typical Max Unit
tRISE tFALL
CML Output Rise Time (20-80%, 100 balanced load) CML Output Fall Time (80-20%, 100 balanced load)
60 60
170 170
ps ps
Notes 6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal. 7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in Figure 6. 8. +20 ppm is required to meet the SONET output frequency specification.
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CYS25G0101DX
Table 9. Jitter Specifications Parameter Description Min Typical[10] Max[10] Unit
tTJ-TXPLL tTJ-RXPLL
Total Output Jitter for TX PLL (p-p)
[9]
0.03 0.007 0.035 0.008
0.04 0.008 0.05 0.01
UI UI UI UI
Total Output Jitter for TX PLL (rms)[9, 11] Total Output Jitter for RX CDR PLL (p-p)[9] Total Output Jitter for RX CDR PLL (rms)[9, 11]
Jitter Waveforms
The Jitter Transfer Waveform of CYS25G0101DX follows. [12].
Figure 4. Jitter Transfer Waveform of CYS25G0101DX
The Jitter Tolerance Waveform of CYS25G0101DX follows. [12]
Figure 5. Jitter Tolerance Waveform of CYS25G0101DX
Notes 9. The RMS and P-to-P jitter values are measured using a 12 KHz to 20 MHz SONET filter. 10. Typical values are measured at room temperature and the Max values are measured at 0 C. 11. This device passes the Bellcore specification from -10 C to 85 C. 12. The bench jitter measurements are performed using an Agilent Omni bert SONET jitter tester.
Document Number: 38-02009 Rev. *K
Page 12 of 17
CYS25G0101DX
Figure 6. CYS25G0101DX Reference Clock Phase Noise Limits
CYS25G0101DX Reference Clock Phase Noise Limits
-75
-85
-95
Phase Noise (dBc)
-105
-115
-125
-135
-145
-155 1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Frequency (Hz)
Switching Waveforms
Transmit Interface Timing
tTXCLKI tTXCLKIDH tTXCLKIDL
TXCLKI
t TXDS tTXDH
TXD[15:0]
tTXCLKO tTXCLKODL tTXCLKODH
TXCLKO
Receive Interface Timing
Document Number: 38-02009 Rev. *K
Page 13 of 17
CYS25G0101DX
Typical IO Terminations
Figure 7. Serial Input Termination
Limiting Amp 0.1 F
OUT+ OUT-
CY S25G0101DX Zo=50
IN+ 100 IN-
0.1 F
Zo=50
Figure 8. Serial Output termination [13]
CY S25G0101DX 0.1 F
OUT+ OUT-
Optical Module Zo=50
IN+ 100 IN-
0.1 F
Zo=50
Figure 9. TXCLKO/ RXCLK Termination
CY S25G0101DX VDDQ=1.5V
HSTL OUTPU T
FRAMER Zo=50 100 100
HSTL INPUT
Figure 10. RXD[15:0] Termination
CY S25G0101DX Zo=50 FRAMER
HSTL INPUT
HSTL OUTPU T
Figure 11. LVPECL Compliant Output Termination
VDDQ=3.3V
RXD[15;0], RXCLK, TXCLKO OUTPUT
FRAMER VDDQ=3.3V 137 Zo=50 80.6 121 LVPECL INPUT
CY S25G0101DX
Note 13. Serial output of CYS25G0101DX is source matched to 50 transmission lines (100 differential transmission lines).
Document Number: 38-02009 Rev. *K
Page 14 of 17
CYS25G0101DX
Figure 12. AC Coupled Clock Oscillator Termination
Clock Oscillator Zo=50
LVPEC L OUTPUT
VCC VCC
130 82 VCC 130 0.1uF 0.1uF
CY S25G0101DX
Zo=50
82
Refcloc k I nter nall y Biased
Figure 13. Clock Oscillator Termination
Clock Oscillator Zo=50
LVPEC L OUTPUT
VCC 130 82 VCC 130 82
CY S25G0101DX
Zo=50
Reference Cloc k Input
Document Number: 38-02009 Rev. *K
Page 15 of 17
CYS25G0101DX
Ordering Information
Speed
Standard Standard Standard Standard
Ordering Code
CYS25G0101DX-ATC CYS25G0101DX-ATXC CYS25G0101DX-ATI CYS25G0101DX-ATXI
Package Name
AT120 AT120 AT120 AT120
Package Type
120-pin TQFP 120-pin Pb-Free TQFP 120-pin TQFP 120-pin Pb-Free TQFP
Operating Range
Commercial Commercial Industrial Industrial
Package Diagram
Figure 14. 120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) with Heat Slug AT120
51-85116-**
Document Number: 38-02009 Rev. *K
Page 16 of 17
CYS25G0101DX
Document History
Document Title: CYS25G0101DX SONET OC-48 Transceiver Document Number: 38-02009 REV.
** *A *B
ECN NO.
105847 108024 111834
Issue Date
03/22/01 06/20/01 12/18/01
Orig. of Change
SZV AMV CGX
Description of Change
Change from Specification number: 38-00894 to 38-02009. Changed Marketing part number. Updated power specification in features and DC specifications section. Changed pinout for compatibility with CYS25G0102DX in pin diagram and descriptions. Verbiage added or changed for clarity in pin descriptions section. Changed input sensitivity in Receive Data Path section, page 6. RXCLK rise time corrected to 0.3 nSec min CML and LVPECL input waveforms updated in test load and waveform section. Diagrams replaced for clarity Figures 1-10. Added two Refclock diagrams Figures 9 and 10. Updated temperature range, static discharge voltage, and max total RMS jitter. Updated the single ended swing and differential swing voltage for Receiver CML compatible inputs. Created a separate table showing peak to peak and RMS jitter for both TX PLL and RX PLL. Added Industrial temperature specification to pages 8, 11, and 15. Added differential waveform definition. Added BGA pinout and package information. Changed LVTTL VIHT min from 2.0 to 2.1 volts. Added phase noise limits data. Removed BGA pinout and package information. Removed references to CYS25G0102DX. Removed "Preliminary" from datasheet Added power up requirements to Maximum Ratings information Revised power up requirements Added Pb-free logo Added Pb-free parts to the Ordering Information: CYS25G0101DX-ATXC, CYS25G0101DX-ATXI
*C *D
112712 113791
02/06/02 04/24/02
TME CGX
*E *F
115940 117906
05/22/02 09/06/02
TME CGX
*G
119267
10/17/02
CGX
*H *I *J *K
121019 122319 124438 1309983
11/06/02 12/30/02 02/13/03 07/27/07
CGX RBI WAI IUS/SFV
(c) Cypress Semiconductor Corporation, 2001 - 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-02009 Rev. *K
Revised July 27, 2007
Page 17 of 17
PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.

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